I2C (Inter Integrated Circuit)

pins – SDA, SCL, GND     -              half duplex
multi master – multi slave
both pins are open-drain and need to be pulled up with resistors
maximum number of nodes is restricted by address space and total bus capacitance of 400uF
data changes only when clock is low
if data line changes high to low when clock is high, it is start condition
if data line changes low to high when clock is high, it is stop condition
in I2C, addresses are 7 bits long
8th bit is used to tell whether to write data to slave or read data from slave
every slave device has an address, generally assigned by NXP
when bus is low, it is pulled up
master pulls sda low, when scl is high – this is start signal
next master writes 8 bit address (7+1)
slave acks by pulling sda low
then 8 bit data is put on sda with msb first
each data byte is acked by pulling sda low by receiving end
if slave is not able to keep up with master clock, it pulls scl low after ack, so gets to know that slae requires some more time and wait till slave releases scl. this is clock stretching
when multiple masters try to write, it monitors clk, if clock is detected on scl, then it waits till stop bit. if both start same time, then one who pulls sda low wins arbitration. for this master always listens and check bus if same bit i.e. 1 is written on bus or not.
data rate typically 100kbps to 400 kbps

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