pins – SCK, MOSI, MISO, SS’, GND - forced
full duplex
one master, multiple slaves – one to many
why slave select SS’ is active low?
master first provides the clock on SCK
then gives low to SS’
if chip select is not low, slave ignores clock on SCK and
signal on MOSI
during each spi clock cycle, full duplex data transmission
occurs.
master sends one bit on MOSI and slave reads it, while slave
send one bit on MISO and master reads it
even if it one directional data transmission is intended,
both side data is exchanged, so forced full duplex
generally master sends msb first, and slave sends lsb first.
they use shift registers
master must select only one slave at a time, otherwise MISO
pin might damage
spi mode define CPOL – clock polarity and CPHA – clock phase
when slave is not selected, its MISO is tri-stated i.e. not
connected
difference between chip-select and output-enable?
what is pull-up and pull-down resistor?
goes over 10mbps, what is max clock speed ?
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